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Unveiling the MIPS Register Set: A Comprehensive Guide

Explore the complete list of MIPS CPU registers, their classifications, and primary functions to understand MIPS architecture.

Understanding the register set is fundamental to programming and comprehending any CPU architecture, and MIPS (Microprocessor without Interlocked Pipeline Stages) is no exception. MIPS processors are known for their streamlined RISC (Reduced Instruction Set Computer) design, which heavily relies on a well-defined set of registers for efficient operation. This article provides a comprehensive overview of all MIPS registers, categorizing them by their function and common usage conventions.

General Purpose Registers (GPRs)

MIPS architecture features 32 general-purpose registers, each 32-bits wide (for MIPS32) or 64-bits wide (for MIPS64). These registers are the workhorses of the CPU, used for storing integer data, memory addresses, and intermediate results during computation. While they are 'general purpose,' MIPS assembly programming adheres to strong conventions for their usage, which are crucial for writing readable and maintainable code, especially when interacting with compilers and operating systems.

flowchart TD
    subgraph MIPS GPRs
        R0["$zero (r0)"]
        R1["$at (r1)"]
        R2_3["$v0-$v1 (r2-r3)"]
        R4_7["$a0-$a3 (r4-r7)"]
        R8_15["$t0-$t7 (r8-r15)"]
        R16_23["$s0-$s7 (r16-r23)"]
        R24_25["$t8-$t9 (r24-r25)"]
        R26_27["$k0-$k1 (r26-r27)"]
        R28["$gp (r28)"]
        R29["$sp (r29)"]
        R30["$fp/$s8 (r30)"]
        R31["$ra (r31)"]
    end

    R0 -- "Always 0" --> Usage0[Constant Zero]
    R1 -- "Reserved for Assembler" --> Usage1[Assembler Temporary]
    R2_3 -- "Function Return Values" --> Usage2[Return Values]
    R4_7 -- "Function Arguments" --> Usage3[Arguments]
    R8_15 -- "Temporary (Caller-saved)" --> Usage4[Temporaries]
    R16_23 -- "Saved (Callee-saved)" --> Usage5[Saved Values]
    R24_25 -- "Temporary (Caller-saved)" --> Usage6[More Temporaries]
    R26_27 -- "Reserved for OS Kernel" --> Usage7[Kernel Temporaries]
    R28 -- "Global Pointer" --> Usage8[Static Data Access]
    R29 -- "Stack Pointer" --> Usage9[Stack Management]
    R30 -- "Frame Pointer / Saved" --> Usage10[Stack Frame / Saved]
    R31 -- "Return Address" --> Usage11[Function Return]

    style R0 fill:#f9f,stroke:#333,stroke-width:2px
    style R1 fill:#fcf,stroke:#333,stroke-width:2px
    style R2_3 fill:#ccf,stroke:#333,stroke-width:2px
    style R4_7 fill:#ccf,stroke:#333,stroke-width:2px
    style R8_15 fill:#cff,stroke:#333,stroke-width:2px
    style R16_23 fill:#cfc,stroke:#333,stroke-width:2px
    style R24_25 fill:#cff,stroke:#333,stroke-width:2px
    style R26_27 fill:#fcc,stroke:#333,stroke-width:2px
    style R28 fill:#ffc,stroke:#333,stroke-width:2px
    style R29 fill:#ffc,stroke:#333,stroke-width:2px
    style R30 fill:#ffc,stroke:#333,stroke-width:2px
    style R31 fill:#ffc,stroke:#333,stroke-width:2px

MIPS General Purpose Register (GPR) Naming Conventions and Usage

The diagram above illustrates the common naming conventions and typical usage for MIPS GPRs. It's important to note that while the hardware doesn't enforce these conventions (except for $zero), adhering to them is critical for interoperability and correct program execution, especially in larger projects or when using standard libraries.

Special Purpose Registers

Beyond the GPRs, MIPS processors include several special-purpose registers that handle specific aspects of CPU operation, such as multiplication/division results, program control, and exception handling. These registers are not directly accessible in the same way as GPRs but are manipulated through specific instructions or by the CPU's internal logic.

HI and LO Registers

These two 32-bit registers (or 64-bit for MIPS64) are used to store the results of multiplication and division operations. A 32-bit multiplication can result in a 64-bit product, which is split between HI (most significant 32 bits) and LO (least significant 32 bits). Division results in a quotient (stored in LO) and a remainder (stored in HI). Instructions like MFHI (Move From HI) and MFLO (Move From LO) are used to transfer their contents to GPRs.

Program Counter (PC)

The Program Counter is a crucial register that holds the memory address of the next instruction to be fetched. It's automatically incremented after each instruction fetch and can be modified by branch, jump, and call instructions to alter the flow of execution. The PC is not directly accessible by software but is implicitly used by all control flow instructions.

Status Register (SR) and Cause Register (Cause)

These registers are part of Coprocessor 0 (CP0), which handles system control and exception processing. The Status Register contains various control bits, including interrupt masks, kernel/user mode flags, and exception handling options. The Cause Register stores information about the most recent exception or interrupt, such as the type of exception and the pending interrupt sources.

Exception Program Counter (EPC)

Also part of CP0, the EPC stores the address of the instruction that caused an exception. When an exception occurs, the CPU saves the PC's value into EPC before jumping to the exception handler. This allows the exception handler to return to the exact point where the exception occurred after processing.

Floating Point Registers (FPRs)

MIPS processors often include a Floating Point Unit (FPU), also known as Coprocessor 1 (CP1), which has its own set of registers for handling single-precision (32-bit) and double-precision (64-bit) floating-point numbers. These are distinct from the GPRs.

MIPS typically provides 32 floating-point registers, named $f0 through $f31. These registers can be used in pairs for double-precision operations. For example, $f0 and $f1 might be used together to store a 64-bit double-precision value. Similar to GPRs, there are conventions for FPR usage, particularly for function arguments and return values (e.g., $f12, $f14 for arguments, $f0, $f2 for return values).

  .data
value1: .float 3.14
value2: .float 2.71
result: .float 0.0

  .text
  .globl main
main:
  lwc1 $f0, value1    # Load single-precision float from memory into $f0
  lwc1 $f1, value2    # Load single-precision float from memory into $f1
  add.s $f2, $f0, $f1 # Add single-precision floats $f0 and $f1, store in $f2
  swc1 $f2, result    # Store single-precision float from $f2 to memory

  li $v0, 10          # syscall code for exit
  syscall             # Exit program

Example of MIPS floating-point operations using FPRs.